ICSS-JC ＆ JEITA establish new Joint Working Group (JWG) to study and examine ‘Chiplet Security’

ICSS-JC (IC System Security - Japan Consortium) has recently established a ‘Joint Working Group (JWG)’ with JEITA (Japan Electronics and Information Technology Industries Association) to study and examine ‘Chiplet Security’.(Chair: Makoto Nagata, Professor, Technology and Innovation, Graduate School of Science, Kobe University). The first meeting was held on Tuesday, 30 September 2025.

This initiative will be jointly advanced by the ‘Hardware Security Study Task Group’ (within the newly established ‘Chiplet Solution Working Group’(set up in August 2025) under JEITA's Semiconductor Standardisation Committee/Semiconductor System Solution Technical Committee) , and the newly established ‘SWG12’ within ICSS-JC.

JWG will initially discuss on overall chiplet security, with ‘Standardisation of HSMs (Hardware Security Modules) in Chiplets’. Collaboration between the two organisations will combine JEITA's ‘expertise in semiconductors’ with ICSS-JC's ‘expertise and track record in IC Chip Security Evaluation and Certification’ will expect rationalised and efficient discussions.